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ESD Process Shrinks I/Os Along Core Path
By Koen G. Verhaege
Silicon real estate is a semiconductor company's most valuable asset. If a company can put more devices on a wafer, it boosts revenues. This has been a major driving force behind the shrinking of feature size. IC cores have shrunk significantly over the past decade. More functionality is now available in smaller silicon area. Just one element of IC design has not been cooperating: the I/O area.
We need input-output transistors to enable communication between small signals within the IC core (measured in microamperes) and the other signals surrounding electronic subsystems (measured in milliamperes). This means that one needs to address the size of the I/O transistors, which come in the form of very wide transistors (hundreds of micrometers, compared with single-micron-sized transistors in the core.
Unfortunately there is more. Electrostatic discharge, which is an IC yield threat, exhibits several amperes of current. Thus, as the mandatory ESD protection design measures are introduced on-chip, size really kicks in.
If you want to provide ESD design protection, you must provide proper ballast to the high-current electrostatic discharge. The traditional approach is to provide ballasting resistance with active silicon spacing in the sensitive devices (mostly NMOS transistors). This solves the problem, but comes at a high expense: Ballast resistance uses significant silicon area, while silicon area is the single most cost-sensitive element in most ICs.
With the advent of some recent silicon-proven design innovations, that is no longer true. Ballast resistance can be built with a very efficient use of area. Semiconductor companies reap the benefits of smaller I/Os, which result in smaller ICs, more ICs per wafer and an increase in revenue per wafer of around $100 or more.
The novel design solution comprises back-end-ballasting (BEB) with segmentation device design, merged ballast circuit layout (MBC) and multifinger circuit design (MFT).
In a typical 0.18-micron CMOS process, when compared with conventional technology, the combination of BEB, MBC and MFT delivered the following:
The silicon design solution is 100 percent CMOS compatible. No process changes and no special or additional masks are required. Actually, the solution is fairly simple, once you let go of three 20-year-old paradigms.
The first paradigm shift is to know that you do not need active-area ballasting or silicide blocking to provide ESD robustness on-chip.
Proper ballasting for ESD robustness does not need to be formed by large silicide-blocked, active-silicon spacing. One can use the process back-end elements, such as contact-to-silicon, contact-to-poly and silicided polysilicon to form a ballasting network. Key to this approach is to introduce 'segmentation' of the ballast resistance: Use multiple parallel high resistors to form a global ESD-robust device with low series resistance, as illustrated in Figures 1 and 2.
This technique not only gives you great ESD performance, it also eliminates the need for silicide blocking.
Analog designers often use silicide blocking for precision resistors. To them the benefit lies in the significantly reduced drain-to-well parasitic capacitance: compare a minimum-size drain diffusion with a 3- to 4-micron active-ballasted drain diffusion, and this works for every active micron of I/O transistor width.
The second paradigm shift is to understand that the ballast area can be shared and thus bigger drivers can be made relatively smaller, not bigger.
Once active-area ballasting is abandoned, one is (fortunately) left with dielectrically isolated resistor segments. It has been silicon-proven that such resistors do not need a minimum-pitch spacing in order to provide the necessary ESD performance. If you double the minimum pitch, you can merge the ballast areas of adjacent transistor fingers and thus make the overall layout of the driver and ESD transistors very compact, as illustrated in Figure 2.
The third paradigm shift is for you not to be concerned about multifinger transistor ESD performance-it can be done quite automatically. Original designs have introduced significant macro-ballasting resistors. Their effect is to build up voltage fast when single fingers conduct relatively small levels of ESD current. More recent designs use dynamic timing circuits to provide a trigger bias to all fingers simultaneously.
An innovation within this novel design solution came from the realization that one does not necessarily have to worry about turning on the entire multifinger transistor as soon as the ESD event hits. When ESD hits, you know at least one transistor finger will trigger into its snapback state to conduct the ESD current. That's a given. Now let's use the nonuniform conduction state of the multifinger transistor to sense that an ESD event is going on. A bias signal can be derived to turn on all fingers. It can be done without any dynamic trigger circuits and it can be done using minimal overall macro ballast. Figure 3 shows a principle circuit, which was silicon-proven for up to 16 fingers of 50-micron NMOS transistors. Other circuits based on the same principle but which are compatible with drive transistors can be designed as well [reference to paper Mergens et al., EOS/ESD Symposium 2001].
This new design approach achieves new technical benchmarks in ESD protection performance and efficiency, and it does a better job of shielding sensitive ICs from shocks that could destroy them and reduce wafer yields.
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© 2001 CMP Media LLC.
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